EMPLOYMENT RECORD – PROFESSIONAL WORK EXPERIENCE

Jan 2012 to present

Associate Professor

Khalifa University for Science, Technology and Research (KUSTAR)

Duties include but not limited to:

Teaching: Graduate courses: Advanced Computer Architecture, Digital ASIC Design. Undergraduate courses: Microprocessors, Advanced Digital Design and Electronic Devices & Circuits II.

Supervised over 22 senior design projects. Assumed the role of ECE SDP coordinator for 3-yaers. Took the role of seminars coordinator for 2-semesters.

Graduated 1-PhD students and 6 Masters Students. Currently supervising 2-PhD students and 2 MSc students.

 

Dec 2010 to April 2012

Design Engineer (Tech Lead)

Apple Corp., Austin, Texas, USA.

Duties include but not limited to:

One of the logic design leads of Apple Lonestar design center. Primarily Digital Design, u-architecture work, RTL coding, work with the integration team, synthesize, CTS, place & route, power closure and timing closure.

 

May 2008 to Dec 2010

Component (Staff) Design Engineer (uArchitect/RTL Design Engineer)

Intel Corp., Austin, Texas, USA.

Duties include but not limited to:

One of the u-architects of the Intel future Atom low power uprocessor (Silvermont). Primarily Digital Design, u-architecture work, RTL coding, work with the integration team, synthesize, CTS, place & route, power closur and timing closure. I own the integer multiplier, the CPU control register bus (CRAB bus), in addition to leading the effort of power reduction on the integer execution cluster.

 

November 2006 to May 2008

Staff Design Engineer

AMD, Austin, Texas, USA.

Duties include but not limited to:

One of the digital design team of the AMD Bobcat low power uProcessor. Primarily Digital Design, recommend architecture changes to meet timing goals, recoding RTL to meet timing, partition design for timing closure and ease of implementation, synthesize, physical synthesize, CTS, PNR and PTSI timing closure.

 

October 2005 to October 2006

Staff Logic Design/Physical Design Engineer

Qualcomm Inc., Austin, Texas, USA.

Duties include:

One of the u-Architects of the QDSP6, Qualcomm next generation Interleaved multithreaded DSP processor. Primarily Digital Design, uArchitecture development, Verilog RTL design, Synthesis, Physical synthesis, Static timing analysis, floorplaning. Also helped to set the PD flow and provided assistance to the PD team on clock tree Synthesis (CTS), Rail analysis, Routing, LVS/DRC, Metal Fill and chip finishing.

 

 July 2001 to October 2005

Senior II IC Design Engineer

Synopsys Inc., Austin, Texas, USA.

Duties include:

Primarily Digital Design, uArchitecture development, Verilog RTL design, Synthesis, Physical synthesis, Static timing analysis, floorplaning, and some experience in clock tree Synthesis (CTS), Rail analysis, Routing, LVS/DRC, Metal Fill and chip finishing. I have u-Architected and performed the digital design of Synopsys I2C DesignWare IP. Worked on many ASIC’s for Synopsys Customers: Northrop Grumman Hawk ASIC , Xemi clock distribution chip, AMD multiport USB2 PHY, ADI Texmex ASIC and SiLabs Mercury chip.

 

November 2000 to July 2001

Staff IC Design Engineer

HAL Computer Systems (A Fujitsu Owned Company), Austin, Texas, USA.

Duties included:

  • Created the top level schematic and integrated the various blocks of a SOI-CMOS9S test chip.
  • Performed functional verification and simulation of various design blocks using TimeMill.
  • Performed HSPICE simulation, verification and timing analysis of clock tree and chip enable tree.
  • Performed DRC, LVS and LPE extraction of custom design blocks.

 

December 1997 to July 2000

Senior Design Engineer (Technical Lead)

Motorola Australia Pty Ltd, Adelaide, Australia.

Duties included:

  • Technical lead role on a project to develop a Verilog synthesizable model for the MCore M210 uController core.
  • Technical lead role on a project to develop Verilog synthesizable models for the following HC08 peripheral modules: SCI, SPI and Timer.
  • Designed synthesizable Verilog RTL models for the SPI, SCI and Timer modules.
  • Transistor level power analysis using the EPIC PowerMill tool.

 

September 1996 – July 1997

Senior Design Engineer

Palestine Engineering Co., Amman, Jordan.

Duties included:

  • Design team key role in a project of four design engineers whose purpose was to develop a uController Based Electronic lift controller system. The outcome of this project was a sixteen floor full-collective lift controller system, it sensed and/or generated 134 field signals coming out from the lift well, lift cabin, calls push buttons, indicating lamps and the machines room.

 

July 1995 – July 1996

Senior Electronic Design Engineer

Technological Industrial Group (TIG), Amman, Jordan

Duties included:

  • Led a team of three engineers, to design and implement a computerized Cement Batching Plant control system including all the electronic and the electrical automation needed for the system.
  • Developed a PC based electronic scale.
  • Developed standalone electronic scale from idea to spec to a working prototype.

 

February 1993 – June 1995

Electronic Design Engineer

Systems and Electronics Design Company (SEDCO), Amman, Jordan.

Duties included:

  • Sole electronic and system level design engineer on the following products:
  1. NEPRAS Board: RS232-Telex Interfacing board.
  2. UNICLIENT Board: A PC Boot ROM card (IBM based) that simulates a solid-state disk.
  3. Telex Dongle: Interface between V28/RS232 signals and 2-wire Telex/Telegraph circuits.
  4. Nadim: A µProcessors-based (Z80) printer Arabization Adapter that converts a Latin-only printer into a Bilingual printer.
  5. EPSON Arabiztion Card: An intelligent µProcessor-based (Z80) card used to Arabize EPSON printers.
  • Developed PAL/GAL digital designs, analysis, optimization, simulation and verification.
  • Developed Assembly and C device drivers and debugging utilities for the aforementioned products.