Primary Skills:

  • Architected, uArchitected and RTL designed: Integer multiplier, floating-point adder, floating-point multiplier, floating-point fused primitives (FMA, FAS and FDP).
  • Developed uArchitecture documents and verification requirements documents.
  • Developed fully synchronous, fully scan compliant, Synthesizable Verilog (V95, V2k1 & System Verilog) RTL models for uController cores, µProcessor cores and uController peripheral modules (SCI, SPI, I2C and Timer).
  • Deep understanding of many DSP algorithms and how to model them in hardware.
  • Performed formal verification, top-level chip integration and created Chip level and module level Floorplans.
  • Performed CTS, place & Route, RLC extraction, LVS, DRC, metal fill and chip finishing.
  • Performed transistor level layout, simulation and timing analysis.
  • Modeled DSP algorithms, designed FIR/IIR filers and modeled software defined radio.
  • Developed ARM-AXI slave, built a Verilog RTL model for the DLX processor and built a Verilog RTL model for a DSP FFT Core.
  • Designed Board level uC/uP mixed signal based circuits.
  • Designed and layout of multilayer high-speed PCBs.


TOOLS – Software skills

Front End Tools:

Synopsys VCS, Design Compiler, PrimeTime, Formality, VERA, Cadence Verilog-XL, Mentor Modelsim and Motorola VCX Verilog simulators, Formality, Verplex/Conformal, Debussy/Verdi,  Xilinx ISE, Synplify Pro, Active-HDL.

Physical Design Tools:

JupiterXT, Physical Compiler, Synopsys ICC, Astro, Astro-Rail, Nanosim, Hercules and StarRCXT.

Transistor Level Tools:

HSPICE, Pspice, Cadence CIS/Composer, Epic PowerMill, Astro-Rail, Calibre and X-Calibre for LVS and LPE extraction, Magic.

System Level Design Tools:  Mathworks Matlab.

  • Developed software and hardware-device drivers using C and Assembly.
  • Developed Make files, Perl, Tcl and basic shell scripts.